1. Technical field
The present invention relates generally to the field of integrated circuit design, particularly to the design of Integrated Circuits (ICs), and Application Specific Integrated Circuit (ASICs), in a system with plural or "mixed" DC voltage supplies.
2. Related Art
The field of low power integrated circuitry is a rapidly developing field of technology. Integrated circuits are continually being made smaller while simultaneously increasing both device speed and circuit density. The miniaturized devices built within and upon a semiconductor substrate are spaced very closely together and the integrated circuit density, that is, the number of transistor elements per unit of surface area, continues to increase significantly. The highest integrated circuit density is currently achieved using Field Effect Transistors (FETs).
A FET is a semiconductor device having a source, gate, and drain arranged such that when a high logic signal voltage is applied to the gate, current may pass from the source to the drain, and the voltage difference between the source and the drain approaches zero. Conversely, the FET does not allow current to pass between the source and the drain when a low logic signal voltage is applied to the transistor's gate. Complementary metal oxide semiconductor (CMOS) circuit elements further limit current usage by employing two complementary FETs (NFET and PFET) arranged gate-to-gate between the voltage supply and ground, which stops the flow of current during operation except during momentary transitions between logical states. The shorter the time that each such logical transition takes, the less current, hence power, is consumed. Therefore, power consumption and heat generation can be reduced by designing CMOS elements to "switch" states in the least amount of time possible. The length of time to require to switch a given transistor from one logical state to the other depends on both the internal characteristics of the transistor and upon the properties of the circuit that drives the gate of the transistor.
A CMOS transistor's gate operates in tandem with a parallel back-gate in a manner similar to a capacitor having a metal oxide dielectric. The larger the transistor is, the larger the area of its gate is, and the more capacitance it has. The more capacitance a transistor has, the more time it will take to "fill up" the capacitance at its gate with electric current from a given driving circuit. Similarly, the more capacitance the transistor has, the longer it will take to discharge to ground the charge stored at its gate. Therefore, smaller CMOS transistor elements are generally faster than larger CMOS transistor elements. It follows that smaller CMOS transistor elements generally consume less electrical power, and generate less heat, than larger CMOS transistor elements, and for this reason, as is more thoroughly explained below, smaller elements are generally preferred where they are otherwise functionally adequate. However, the smaller a given CMOS transistor is, the slower it will be able to fill (or empty) the gate capacitance of the next CMOS transistor or transistors which it drives. Therefore, large transistors are generally required to drive large transistors, and small transistors are generally adequate only to drive small transistors.
Generally, the fastest CMOS circuits are those which are designed to perform the required logical operation with the smallest transistors and with the fewest number of transistor elements. In designing integrated circuits, the size of a given transistor performing a particular function is generally reduced until its function would become impaired. If a given transistor can be eliminated from a known circuit design entirely without impairing the circuit's operation, that ultimate reduction of transistor size is generally considered to be an improvement in the design. In general, the more transistor elements there are in the path of a given signal, the slower that signal will propagate through the circuit to its destination, and the more power will be consumed. The necessity for level-shifting output buffers is generally due to a relentless pursuit by circuit designers of reductions of power consumption, which also may be accomplished by lowering the operating voltage applied to the transistors in the core logic, as is more thoroughly explained below.
Power consumption in electronic devices can be approximated by the equation P=VI (i.e., Power "P"=Voltage "V" times Current "I"). Power consumption is equal to the value of the DC supply voltage (e.g., "Vdd") multiplied by the amount of current (e.g., "I") flowing from the supply through the circuit's transistors. At any given moment in time, total current "I" consumed by a chip is generally equal to the sum of the smaller currents flowing through the numerous transistors and other circuit elements on the IC. The power consumed by a circuit in operation is transformed into heat within the circuit, which then must be continually dissipated in order to avoid thermal breakdown and failure of the circuit.
As the integrated circuit density on a chip increases, the amount of power consumed and heat generated per unit of area by the integrated circuits on the substrate increases proportionally. The integrated circuit industry has changed from TTL to CMOS in order to decrease the current consumption, thereby reducing power consumption and heat generation.
In digital CMOS systems, power consumption increases approximately proportionally with the frequency of the switching operation of the circuit. However, the minimum frequency of switching operation is usually constrained by logical and performance requirements and therefore reduction of switching frequency is not always available as a way to reduce power consumption.
To further decrease power consumption, and therefore heat generation, it is desirable that the operating voltage be reduced. Power consumption can be decreased by lowering the voltage supply (such as from five volts to three and one third volts) which also proportionally decreases the amount of current consumed. Heat generation is approximately proportional to the square of the power supply voltage at which the logic circuit is operating. Therefore, a decrease in a circuit's DC supply voltage from five volts to three volts will approximately decrease power consumption by forty percent.
The amount of heat generated is of concern to chip designers, manufactures and end-product designers because cumbersome heat sinks and customized heat-dissipating circuit packaging may become necessary to prevent a small fast chip's temperature from rising above its rated operational temperature limit. Further, the heat released is generally wasted energy, and many devices containing integrated circuits typically operate on limited stored power. One familiar example is a portable computer operating on battery power. As the heat generation in a device increases, battery life decreases. Heat itself may also adversely affect the operational life and reliability of the electronic device. Therefore, reducing the heat dissipated by a given integrated circuit is important in the design of integrated circuits and the devices into which they are incorporated.
As explained above, one way to decrease the power consumption of a circuit is to reduce the voltage at which the circuit operates. However, decreasing the operational voltage level of one circuit in a system can create compatibility problems where some other integrated circuit or other device is designed to operate at predetermined incompatible specific voltage level, or is accessible only via a bus that operates optimally at a different (e.g., higher) voltage logic level. For example, some circuits within a chip may operate at low voltage core-logic level to reduce power consumption and to interface with other chips operating at the same low voltage, while other circuits in the same chip may operate at higher voltage levels to interface with a higher logic voltage chip or bus or to operate an electro-mechanical device. Also, there are many existing integrated circuits that cannot have their operating voltage altered, yet, newer lower voltage circuits must interface with them. For example, if core logic "one" voltage were reduced from a nominal 5 volts to 3.3 V, the logic "one" value represented by 3.3 V would ordinarily be insufficient to properly drive another transistor circuit operating from a 5 V power supply. The 3.3 V logic "one" input to a 5 volt CMOS circuit would cause a prolonged transitional (i.e., conducting) state potentially resulting in damaging shoot-through currents in the CMOS circuits tied to a 5 volt supply. The rise, fall, and propagation times of signals would be detrimentally affected by the difference between core logic voltage and the circuits operating at a higher logic voltage. Therefore, to lower the voltage of integrated circuits and to consume less power, while still enabling their interaction with existing hardware components operating at a different voltage, some form of voltage level-shifting interface circuit (e.g., level-shifting buffer circuit) is required.
In general, the related art has provided a variety of voltage level-shifting interface circuits for translating lower core-logic signal levels into higher voltage signal levels and vice versa. This is because the trend in the industry has been to repeatedly decrease the core-logic voltage levels implemented in integrated circuits, while bus or pin interface logic voltages on the periphery of the same chip remain at higher levels.
Consequently, many complementary metal oxide semiconductor (CMOS) integrated circuits require more than one power supply per chip. Such designs are known in the art as "split rail designs." For instance, a split rail design is utilized when the internal or core-logic voltage, VDDIN, operates at a different (e.g., lower) voltage level than the input/output (I/O) interface voltage or output driver voltage, VDDOUT. The integrated circuit core voltage, VDDIN, applied to a given circuit may be fixed or variable depending on the integrated circuit technology, design factors, and by the performance requirements and the power supply and heat dissipation characteristics of the chip.
A conventional split-rail IC design creates many design challenges that must be addressed by integrated circuit designers. For a typical split rail integrated circuit to operate properly, it must be designed to operate within all specified ranges of frequency, core voltages and higher external voltages. For CMOS Input/Output (I/O) Integrated Circuits (ICs) to operate with a core voltage, (e.g., VDDIN as in the FIGS. 1-6), that is different or lower than the output or interface voltage, (e.g., VDDOUT as in the FIGS. 1-6), signal voltage level shifting between core logic functions and the output driver control circuitry (also referred to as "pre-drive" circuitry), is required. The level shifting circuit must level-shift the voltage (e.g., VDDIN) of the core signals that control, (i.e., "turn on" and "turn off"), the output driver circuit that is typically referenced to the higher voltage (e.g., VDDOUT).
In the related art of FIG. 1, level shifters in the DATIN (i.e., DATa INto the level-shifting output buffer) path and the OENBAR (i.e., Output-ENable not) path perform that function of level shifting the core logic signal voltage levels for the predrive NAND and NOR gates. In turn, the predrive NAND-gate and NOR-gate (not to be confused with the gates of individual transistors comprising the NAND-gate and NOR-gate) control the transistors (150 and 151) of the output driver stage. Please note that in the all the figures (i.e., FIGS. 1 through 6) wires (a/k/a lines and conductors) drawn crossing over do not connect unless the cross-over is highlighted by a darkened circle such as that at node/line 110. Conversely, wires that join at a "T" are understood to represent a connection and may also be highlighted by a darkened circle. In FIGS. 1-6, PFET transistors are drawn as PFET transistor 150 is drawn and the "back-gate" of each PFET is presumed to be tied to the supply voltage (VDD) unless indicated otherwise. In FIGS. 1-6, NFET transistors are drawn as NFET transistor 151 is drawn and the "back-gate" of each NFET is presumed to be tied to ground unless indicated otherwise. In discussing the figure of the related art and subsequent figures depicting embodiments of the invention, it should be recognized by persons skilled in the art that similarly arranged circuit components are presumed to perform the same or similar functions in each figure, allowing for design variations in physical size of individual transistors and variations in signal characteristics. Such variations are highly dependent upon the IC designer's application requirements and are not easily depicted in the diagrams. Where elements in the figures are referred to by the letter "x" appended to two numerical digits, (e.g., x50) it is to be presumed that elements in each of the figures (e.g., Figure "x"=1, 2, 3, 4, 5, 6) that have the same last two digits are of similar kind and perform the same or similar function in their respective circuit. For example, transistor x50 is a PFET transistor in each of FIGS. 1, 2, 3, 4, 5, 6, meaning that PFET transistors 150, 250, 350, 450, 550, 650 are PFET transistors performing the same or similar functions in their respective circuit, and may all be referred to by "x50."
The tristate output buffer of the related art, shown in FIG. 1, generally includes three stages: a level-shifting stage 106 comprised of one level-shifter for each core logic signal (e.g., DATIN and OENBAR), each comprised of a signal-complementing inverter (e.g., 170 and 171 for DATIN; 176 and 177 for OENBAR) and a cross-wired transistor circuit (e.g., 166, 167, 168, 169 for DATIN; 172, 173, 174, 175 for OENBAR); an output driving stage 109 (e.g., comprised of P-type pull-up transistor 150 and an N-type pull-down transistor 151); and a single predrive stage 108 including core signal-combining circuitry (e.g., a NAND-gate pre-driver comprised of transistors 152, 153, 154, 155, and a NOR-gate pre-driver comprised of transistors 156, 157, 158, and 159) to tristate the output driving stage 109 when the output buffer is not enabled by the core logic signal OENBAR. It would be apparent to persons skilled in the art that in the case where the core logic circuit is designed to provide a pair of synchronized complementing signals (e.g. OENBAR plus OEN) to the output buffer, the complementing inverter of the level-shifter in that path (e.g., 176 and 177) could be eliminated from the level-shifting stage of the output buffer. Signal OENBAR on node/line/conductor 103 is the signal from the core logic that tristates the output driving transistors x50 and x51.
In the case that the output buffer is tristated, OENBAR is logical "one." OENBAR is inverted by a level-shifter's signal-complementing inverter (comprised of transistors x76 and x77) to generate OEN-equivalent (i.e., OENBAR-complement) signal at line/conductor x04. The level shifter in the OENBAR path asserts a level-shifted OENBAR equivalent signal at node/line/conductor x23, and asserts a level-shifted OEN-equivalent (i.e., OENBAR-complement) signal at node/line/conductor x22. When signal OENBAR is a logical "one," then signal OEN (i.e., Output-ENable) is a logical "zero." The level-shifted OENBAR signal is input to the NOR-gate pre-driver at the gates of transistors 157 and 158. In this case OENBAR is a logical "one" and forces the NOR-gate output x11 to be a logical "zero." Thus, transistor x51 is turned "off" because the gate voltage of NFET x51 is then ground (e.g., 0 V).
Similarly, signal OEN (i.e., OENBAR-complement) on line x04 is level-shifted and driven to the NAND-gate pre-driver at transistors 154 and 152 via line/conductor 122. In this case OEN is a logical "zero" and the NAND-gate output x10 is forced to a level-shifted logical "one" (e.g. VDDOUT). Thus PFET transistor x50 is turned "off" because the its gate voltage is VDDOUT volts.
Therefore, for the case that OENBAR is a logical "one," output transistors x50 (e.g., 150, 250, 350, 450, 550 and 650) and x51 (e.g., 151, 251, 351, 451, 551, 651) are both "off" thereby tristating the output buffer.
In the case that the output buffer is turned "on" and not tristated, OENBAR on lines x03 and 123 is a logical "zero." OEN on lines x04 and 122 is a logical "one." The NAND-gate pre-driver is enabled and acts like an inverter of the level-shifted DATIN-equivalent signal asserted on line 131. Similarly the NOR-gate pre-driver is enabled and acts like an inverter of the level-shifted DATIN-equivalent signal asserted on line 131. If DATIN (e.g., on lines x02 and 131) is a logical "one," both the NAND-gate pre-driver output x10 and the NOR-gate pre-driver output x11 are logical "zero." This turns "on" PFET transistor x50 and keeps or turns NFET transistor x51 turned "off." The output at x01 (e.g., 101, 201, 301, 401, 501 and 601) is charged towards VDDOUT to represent a logical "one." In the case that DATIN (i.e., on lines x02 and 131) is a logical "zero," both the NAND-gate pre-driver output x10 and the NOR-gate pre-driver output x11 are logical "one." This turns "on" NFET transistor x51 and keeps or turns PFET transistor x50 turned "off." The PAD output x01 is discharged towards ground to represent a logical "zero." To conserve power, the core logic that asserts the signals OENBAR on line x03 and DATIN on line x02 may have the power supply voltage (e.g., VDDIN) reduced (e.g., below VDDOUT) either dynamically or permanently.
While the conventional three-stage configuration of the related art of FIG. 1 is often adequate to ensure that the output driver's PFET is completely shut "off" when a logical "one" is present on nodes 131, 122, and 110, the process of designing an operational physical IC with the conventional three stage configuration to perform the level shifting output buffer function is difficult.
The conventional three stage output buffer's limitations also can generate delay and/or duty cycle penalties in circuit design because of the large size of the transistors of the level-shifters (i.e., 166, 167, 168, 169 and 172, 173, 174, 175) that are required in the conventional buffer to drive the NAND-gate and NOR gate. The NAND and NOR gates typically have large transistors in order to drive the typically large, low impedance, output driver transistors (x50 and x51). Thus, the large size of transistors of the NAND and NOR gates of the conventional predrive stage present a large capacitive load to the level shifter(s) in the output offer of the related art in FIG. 1. As the size of the transistors in the level shifter (e.g., x66, x67, x68, x69) are increased during physical output buffer design to drive this load, the delay into and through the level shifter increases. Also corresponding to the larger size of the transistors in the level shifter(s), larger transistors are required in the core of the IC chip to interface with the larger transistor gates of the level-shifting stage.
Further, the design of an operable output buffer becomes more difficult in the related art of FIG. 1 because the large PFETS (e.g., 167 and 166) must overcome the large NFETS (e.g., 168 and 169), to change logic states at the level shifter output nodes/lines (e.g. 131, 132, 122, 123). Designing a physical output buffer circuit of the related art to have balanced rising and falling transitions seen by the NAND and NOR gates is difficult, which in turn makes it difficult to balance the rising and falling transitions seen by the gates of the transistors of the output driver stage (x50, x51).
All of these problems mean that physical IC design using the level shifting output buffer of the related art of FIG. 1 has unnecessary and undesirable delay penalties and duty cycle (balancing) penalties that are far from trivial to overcome. Additionally, the multiple larger transistors within the level-shifters of the related art by themselves consume more power than they would if they were smaller in size. The larger transistors of the level-shifting stage of the related art of FIG. 1 also put a larger (capacitive) load on the circuits of the core logic connected to the output buffer of the related art. Larger level-shifting transistors therefore add signal propagation delay from the core and/or require larger transistors within that core circuitry which consume more power than need be consumed. In an IC chip having a multiple (e.g., dozens) of pins or interfaces each having a conventional three-stage level shifting output buffer of the related art of FIG. 1, the finite amount of power unnecessarily wasted by each such output buffer is multiplied by the number of such buffers on the chip. There is a universal need in the field of ASIC design to reduce power consumption however possible where such can be accomplished without impairing the performance of the circuit.